It is generally recognized that some semiconductor devices are susceptible to damage from electrical overstress conditions (EOS). These conditions occur when current or voltage ratings for a circuit are exceeded. Exemplary electrical overstress conditions include electrostatic discharge (ESD), transient conditions, incorrect polarity connections, etc. The electrical overstress conditions are characterized by over-voltage and over-current stress events.
Progress in VLSI technology has resulted in smaller and smaller integrated geometry in integrated circuits. As devices become smaller, they also become more sensitive to damage from electrical overstress conditions. Protecting a device from EOS damage is becoming more and more difficult as circuits are now manufactured with numerous layers of thin film materials. More layers result in a more complicated problem to be solved.
Overcoming electrostatic discharge conditions continues to increase in importance as the sensitivity of semiconductor devices increases. Electrostatic charge (ESC) can accumulate in a body and damage semiconductor devices if the body is brought into contact with a semiconductor device. For example, a person may accumulate electrostatic charge by walking across carpeting. The accumulated electrostatic charge can be imparted to semiconductor devices touched by the individual. Some semiconductor devices are sufficiently sensitive that the resultant flow of charge imparted to the device results in permanent damage to the semiconductor device.
Accordingly, it is highly desired to protect semiconductor devices from electrostatic discharge and other electrical overstress conditions. Some solutions have attempted to minimize the accumulation of electrostatic charge to prevent electrostatic discharge. Exemplary solutions have included utilization of protective clothing such as shoes, smocks, etc. for workers in the semiconductor industry. Such approaches may alleviate the problem of electrostatic discharge to some extent but consumers may not be aware of the potential damaging effects of electrostatic discharge upon the electronic components being handled.
Other approaches for abating electrical overstress conditions and electrostatic discharge events with regard to electrical components have included providing electrostatic discharge components within the electrical or semiconductor components themselves.
It is known to provide mixed signal systems on a single integrated circuit. More particularly, it is possible to include both analog and digital circuits on the same integrated circuit. In such circuits, it is desirable to impede digital noise from reaching the analog circuit. In such circuits, the voltage supplies may be the same or may be different.
Traditionally, ESD protection devices have been constructed for the input and output pads of devices to absorb sudden ESD surges. However, such ESD protection devices are designed for devices with a single power supply. For integrated circuits with mixed signals, multiple independent power supply rails are required to isolate different circuit functions. Adequate ESD protection mandates a clamp circuit between different circuit functions to provide a discharge path between pads. Such a clamp circuit requires a large amount of area on the die. With each additional power supply rail, the area required becomes correspondingly larger.
In such an integrated circuit, multiple independent power supply busses are required to accommodate the requirement of isolation between the various circuit functions. It should be noted that there are interacting signals between the different circuit blocks to provide total system functionality. When different circuit blocks on a mixed signal integrated circuit operate on different supply domains, there must be protection structures incorporated between all power and ground supply rails (in addition to protection circuitry within any circuit block) to guard against damage caused during any ESD stressing between the terminals of different circuit blocks with unrelated power rails. Unfortunately, protection structures between different supply domains counteracts with the requirement of isolation between different supply domains.
FIG. 1 shows a typical prior art circuit arrangement in a mixed signal integrated circuit 10 and its ESD protection scheme. The integrated circuit 10 has multiple functional blocks with respective supply domains. These functional blocks 11, 12, and 13 are labeled "Circuit 1," "Circuit 2," through "Circuit N." The supply and ground rails for these blocks respectively are labeled "VDD1, VSS1," "VDD2, VSS2," through "VDDN, VSSN." Each circuit 11, 12, and 13 has no input or multiple input terminals and no output or multiple output terminals. The input/output terminals may be bi-directional. In FIG. 1, the inputs/outputs (I/O) of the circuits 11, 12, and 13 are represented by terminals 14, 15, and 16. What is not shown in the figure, for simplicity, are the interacting signals between circuit blocks that are within the integrated circuit with no external connection. The circuitry is built as a die on a semiconductor substrate and die pads 17, 18, and 19 provide external connections for the circuits 11, 12, and 13.
To protect against an ESD stress event between any two die pads, there should be a high current path between those pads. This is a basic requirement for preventing ESD damage. ESD protection devices 20 labeled "ESD DEVICE" provide this current path during ESD stressing. Each supply domain has an ESD device 20 between its VDD and VSS, between its I/O and VSS, and between its I/O and VDD. Note that these ESD protection devices can be of many different types, such as: grounded gate NMOS, diode connected PMOS or NMOS, p+/well diode, n+/substrate diode, Zener diode, or SCR based clamp. It should also be noted that depending on the type of ESD protection device used between the I/O and VSS, the ESD protection device between the I/O and VDD may be omitted in some designs.
For protection between the supply domains and to provide high current paths, there are cross-coupled ESD devices between each VDD and other VSSs as shown in the FIG. 1. In a usual die the different VSSs are connected together through substrate resistance 21, 22, and 23 indicated as RSUB. The values of the resistances 21, 22, and 23 depend on the type of substrate material used, and geometry of the circuit layout. Note that the values of the resistances 21, 22, and 23 can be the same or different.
Back to Back (or antiparallel) diodes 24, 25, and 26 (BBD) between the different VSSs are also required for ESD protection. The diodes provide a high current path during stress between circuit block pads (e.g., a supply die pad 27, 28, 29, 30, 31, or 32, or I/O pad 17, 18, or 19) of unrelated supply domains. Without the Back to Back diodes 24, 25, and 26, current may be limited by a high substrate resistance, causing a high voltage build up across the substrate, resulting in damage to the IC.
The integrated circuit (IC) die is usually seated in a housing or package. FIG. 2 shows such a typical case 33 for a plastic quad flat pack package. Die pads 17, 18, 19, 27, 28, 29, 30, 31, and 32 are connected to lead frame pins 34 by bond wires 36. Note that there are various kind of packages for ICs that conceptually have similar arrangements. The IC is connected to some sort of circuit board as its final circuit carrier through its package pins. The bond wires 36 and package pins 34 (or in general package terminals if not pins) have a finite amount of electrical impedance. These impedances are usually very inductive. These impedances are shown by ZVDD1, ZVDD2, ZVDDN, ZVSS1, ZVSS2, and ZVSSN in FIG. 1 for supply rail die pads 27, 28, 29, 30, 31, and 32. Note that similar bond wire, and pin connections, and impedances exist for the I/O die pads 17, 18, and 19. These impedances are not shown since they are not relevant to the invention.
Because of these finite impedances ZVDD1, ZVDD2, ZVDDN, ZVSS1, ZVSS2, and ZVSSN, even if the circuit board power supplies and circuit board supply ground are very quiet, during normal operation of IC, there is noise generated on the VDDs and VSSs of different circuit blocks based on the nature of their functionality. As a result, noise from a noisy VDD or VSS can couple through ESD devices or BBDs to other quiet circuit blocks in the configuration of FIG. 1.
The lower frequency noise usually coupled through the conductive path in ESD devices 20 and BBDs 24, 25, and 26 and the higher frequency noise is transferred by capacitance coupling through the parasitic capacitance of the ESD devices and BBDs. This noise coupling phenomena is well known and appreciated by those skilled in the art. Reducing the amount of noise coupling is one of the design challenges in mixed-signal IC design.
The degree of the coupling between the different supply domains depends on the nature of ESD devices 20 and BBDs 24, 25, and 26 (this is almost uncontrollable by designers for a given process technology) and the values of the ZVDDs and ZVSSs. To reduce the amount of noise coupling, the values of ZVDDs and ZVSSs must be reduced. This can be done by having a better package, using lower inductance pins or using multiple die pads and package pins for each of the VDDs and VSSs. However, this is not trivial to accomplish for a given design with a limited number of package pins.
Thus, a drawback of the circuit of FIG. 1 is that noise generated in one supply domain is easily transmitted to an adjacent supply domain. Further, the level of attenuation is much lower than the attenuation provided in the circuit of the invention, described below. Another drawback is the consumption of surface area on the die. To provide ESD protection, cross-coupled ESD devices and BBDs should be provided between every two circuit blocks on the integrated circuit. However, this would take up too much surface area and would be difficult to arrange on the die as the number of supply domains increase.
Therefore, there exists a need to provide protection from electrical overstress conditions while overcoming the drawbacks associated with the prior art.